Pushing the boundaries of Moore’s Law through custom RISC-V vector extensions, AI neural processing units (NPUs), 2.5D/3D chiplet interconnects, and sub-3nm design methodologies.
R&D Focus Area 01
Investigating domain-specific instruction set extensions (ISA) on open-standard RISC-V cores. Our research focuses on optimizing matrix multiply-accumulate (MAC) throughput for on-device edge AI inference with minimal silicon footprint.
R&D Focus Area 02
As monolithic dies reach reticle limits, chiplet-based modular architectures become essential. We are developing low-latency, high-bandwidth die-to-die physical layer interfaces compliant with UCIe (Universal Chiplet Interconnect Express) standards.
R&D Focus Area 03
Transitioning from FinFET to Gate-All-Around (GAA) nanosheet architectures introduces novel parasitic RC effects and self-heating concerns. Our R&D team develops predictive timing closure scripts and thermal-aware floorplans.
R&D Focus Area 04
Silicon-level cryptographic security hardening against Differential Power Analysis (DPA), clock glitch attacks, fault injection, and physical probing.